1. Field
Embodiments of the present invention relate to a driver for a semiconductor memory such as, for example, a memory cell of PRAM or ReRAM and a driving method thereof. More particularly, embodiments of the present invention relate to a driver for a semiconductor memory, which is capable of improving a write speed by instantly charging parasitic capacitance of each memory cell in the semiconductor memory, and a driving method thereof.
2. Description of the Related Art
As information and communication technology evolves at an increasingly faster rate, the need for a multi-media device capable of performing an interactive communication has started to emerge. For such a device, a semiconductor element having an ability of processing a large amount of information at a high speed is required. Key issues to performance improvement of the device include an ultra-high speed operation, an ultra-high integration density, and a power saving function of a memory element serving as a core part of the system. Particularly, the need for development of a nonvolatile memory device capable of accomplishing the ultra-high integration density has been gradually increasing. A conventional DRAM has a unit cell having a 1-transistor/1-capacitor structure. However, as a size of the unit cell decreases to increase an integration density, it has become increasingly difficult to fabricate the conventional DRAM memory while maintaining a high yield. As a result, the need for developing a new type of a nonvolatile memory to replace the conventional DRAM arises.
Various types of next-generation memories are currently under development to combine characteristics of a high integration density and low power consumption of DRAM with a nonvolatile characteristic of flash memory and a high-speed operation characteristic of SRAM. For instance, the next-generation memories may include phase change RAM (PRAM), nano floating gate memory (NFGM), resistance RAM (ReRAM), polymer RAM (PoRAM), and magnetic RAM (MRAM). However, in the PRAM and PoRAM, since parasitic capacitance may exist in each cell and wiring elements connected to the cell, a write delay may occur. The write delay impedes a high-speed write operation.
In order to resolve the write delay issue, a conventional current driving method has been used. In the conventional current driving method, a charge current is instantly provided to pre-charge parasitic capacitance, thereby reducing a data writing time.
However, this conventional method is highly likely to result in a voltage overshoot or the like during the pre-charge process. On the other hand, when the voltage overshoot is intended to be prevented, it is difficult to obtain a desired data write speed.